1. Field of the Invention
The present invention relates to a method and related circuit for increasing network transmission efficiency of a network interface circuit, and more particularly, to a method and related circuit which can increase a data up-dating rate of a memory in a network interface circuit for increasing network transmission efficiency.
2. Description of the Prior Art
When servers, terminals, and computers located in different areas are connected by a network, data, statistics, and video signals can be transmitted by means of electronic signals through the network. This breaks the limitation of area for communicating knowledge, technologies, and data. Therefore the structure of a network has become an important topic of interest in the modern information society. In addition, IT vendors are working on the development of advanced network transmission equipment. Due to promotion of network transmission efficiency, network service also becomes an important issue.
In general, network users utilize a computer with a network interface card for accessing data of a network service. Please refer to FIG. 1. FIG. 1 shows a diagram of a computer 10 with a prior art interface circuit 20. Besides the network interface circuit 20, the computer 10 includes a CPU 14, a north bridge 16A, a south bridge 16B, a display card 18B, a display 18A, a system memory 22, and peripheral devices 24. The CPU 14 is utilized for controlling the operation of the computer 10. The system memory 22 is a RAM for temporarily storing necessary data, statistics, and program codes when the CPU 14 is working. The display card 18B processes image data to display the operations of the computer 10 in the form of graphics on the display 18A. The north bridge 16A manages the data transmission from the CPU 14 to the display card 18B and to the system memory 22, and vice versa. The network interface circuit 20 could be a network interface card (NIC) to make the computer 10 access data of a network 12. The peripheral devices 24 could includes input devices such as a keyboard and a mouse, non-volatile storage devices such as hard disks and video disc players, and signal processing circuits such as sound cards. The south bridge 16B manages the data transmission through a bus from the CPU 14 to the peripheral devices 24 and to the network interface circuit 20, and vice versa.
The network interface circuit 20 includes a memory access circuit 26, a memory 28, and a medium control module 30. The medium control module 30 includes a buffer 32, a medium access circuit 34, and a transmission circuit 36. The memory access circuit 34 could be a direct memory access (DMA) circuit for directly accessing the data stored in the system memory 22. Data of the system memory 22 accessed by the memory access circuit 26 can be temporarily stored in the memory 28. A plurality of memory units 38 in the memory 28 provides a fixed memory capacity, respectively. The memory capacity of memory units 38 is four bytes. The memory 28 could be a first-in-first-out (FIFO) memory; that is to say, data stored first in the memory 28 is the first to be read from the memory 28. Similarly, the buffer 32 in the medium control module 30 includes a plurality of memory units 40 for providing a fixed memory capacity as memory units 38 do. The medium access circuit 34 transmits data stored in the buffer 32 to the network 12 (another computer, or a hub) by means of signal processing and modulation through the transmission circuit 36.
As is known in the art, data transmitted through network has to be divided into many packets for the management of data transmission. For instance, a header of a packet indicates which network interface circuit sent out the packet and to which network interface circuit the packet is to be sent. A check code of a packet enables a remote computer receiving the packet to inspect for transmission errors. If a transmission error occurs or if a packet is not received correctly, the data will be re-transmitted in another packet. Headers and check codes of packets are controlled by the medium access circuit 34.
Please refer to FIG. 2. When the prior art network interface circuit 20 transmits a packet to the network 12, the procedure 100 is executed. The procedure 100 includes:
Step 102: Start. When the CPU 14 transmits data in packet form to the network 12, the procedure 100 is executed by the network interface circuit 20.
Step 104: The memory access circuit 26 receives the corresponding packet data (“packet data” corresponds to all data of a certain packet; “packet data” differs from “packet” which is transmitted through the network) and stores it in the memory 28. The memory access circuit 26 receives the packet data from the system memory 22 through the bus controlled by the south bridge 16B, the packet data being transmitted from the CPU 14 to the network 12.
Step 106: According to the rule of first-in-first-out, the medium control module 30 moves the packet data stored in the memory 28 into the buffer 32. Then the medium access circuit 34 transmits the packet data stored in the buffer 32 to the network 12 through the transmission circuit 36. The buffer located in the medium control module 30 coordinates the accessing speed of the memory access circuit 26 and the transmitting speed when the medium access circuit 34 transmits data to the network 12. The memory access circuit 26 receives data through the bus of the computer 10, and stores data into each memory unit 38 in the memory 28 sequentially. Therefore the speed that the memory access circuit 26 stores data into the memory 28, in other words, data capacity of the memory access circuit 26 in a unit time, is quite the same as the transmitting speed of the bus in the computer 10. Besides, the speed when the medium access circuit 34 transmits data to the network 12, in other words, data capacity of the medium access circuit 34 in a unit time, depends on the traffic in the network 12 (such as network bandwidth). Due to the difference between the accessing speed of the memory access circuit 26 and the transmitting speed of the medium access circuit 34, the buffer 32 must be set in the medium control module 30. When the speed of the memory access circuit 26 accessing data from the system memory 22 is faster than the speed of the medium access circuit 34 transmitting data to the network 12, the medium control module 30 temporarily stores some data read from the memory 28 (such as a part of some packet data) into the buffer 32, and the medium access circuit 34 will transmit the data to the network 12 with a slow speed. If the memory 28 stores a lot of un-transmitted data, the memory 28 will send a signal to the memory access circuit 26 to stop storing data into the memory 28. And after the medium access circuit 34 transmits the un-transmitted data stored in the memory 28 to the network 12, the memory 28 will release more memory capacity for enabling the memory access circuit 26 to continue accessing data from the system memory 22 to the network 12 and temporarily store data in the memory 28.
Step 108: After the medium access circuit 34 completely transmits all data of a packet to the network 12, the medium access circuit 34 will send out a transmission done signal to the memory 28.
Step 110: In the prior art, after receiving the transmission done signal of the medium access circuit 34, the memory 28 sends an interrupt request signal to the memory access circuit 26. Of course, the memory 28 could include a memory control circuit for controlling the operation of the memory cells in the memory 28 and the operation of the interrupt request signal. However, for different configuration, the circuit for controlling the operation of the interrupt request signal could be outside the memory 28. Therefore, it does not affect the character of the prior art that the next packet is inputted after the previous packet has been transmitted into the network.
Step 112: The memory access circuit 26 sends an interrupt signal to the CPU 14 according to the interrupt request signal for requesting the CPU to continue transmitting another packet data. Next, the procedure 100 returns to step 104. The memory access circuit 26 continues to access new packet data from the system memory 22 according to the indication of the CPU 14 for repeating steps 104 to 106, transmitting a new packet to the network 12.
In order to explain the procedure 100 more clearly, please refer to FIG. 3 to FIG. 7. FIG. 3 to FIG. 7 show the related data location when the computer 10 in FIG. 1 executes the procedure 100. As shown in FIG. 3, suppose that the network interface circuit 20 is ready to transmit a packet to the network 12, the memory access circuit 26 will read the corresponding packet data from the system memory 22 and store it in the memory, as in steps 102 to 104. And suppose that the packet data is composed of five sets of data Dp1 to Dp5 in turn, each set occupying a memory unit 38. According to the rule of first-in-first-out, the first set Dp1 of the packet data is first stored in the memory 28, and then sets Dp2 to Dp5 are stored in the memory 28 sequentially. As shown in FIG. 4, the set Dp1 first stored in the memory 28 will be first output into the buffer 32, and then sets Dp2 to Dp4 are output into the buffer 32 sequentially, as in step 106.
As shown in FIG. 5, the medium access circuit 34 transmits the data of sets Dp1 to Dp4 to the network 12 sequentially. At the same time, the data Dp5 is output from the memory to the buffer 32 and transmitted by the medium access circuit 34 to the network 12 for forming a complete packet of sets Dp1 to Dp5. As shown in FIG. 6, after the medium access circuit 34 completely transmits the data of sets Dp1 to Dp5 to the network 12, the procedure 100 accomplishes step 106 and goes to step 108, the medium access circuit 34 sending a transmission done signal 42 to the memory 28. Next, in step 110, the memory 28 sends an interrupt request signal to the memory access circuit 26 according to the transmission done signal 42. In step 112, the memory access circuit 26 sends an interrupt signal according to the interrupt request signal 44 for requesting the CPUs indication on how to get another new packet data and for transmitting the new packet data to the network 12 through the memory access circuit 26, the memory 28, the buffer 32, the medium access circuit 34, and the transmission circuit 36. As shown in FIG. 7, suppose that a new packet data includes sets Dp6, Dp7, Dp8, Dp9, and Dp10. These sets are stored in the memory sequentially, and the data Dp1 to Dp5 originally stored in the memory 28 are released for storing the new packet data. For instance, as shown in FIG. 7, the memory units originally storing the data Dp1 and Dp2 are overwritten and store the data Dp9 and Dp10 of the new packet data under a recycling memory unit operation, respectively. At that time, the procedure 100 returns to step 104 for starting transmitting new packet data.
One of the drawbacks of the prior art is lower efficiency of network transmission. As mentioned above, after all the data of a packet is transmitted to the network 12 by the medium access circuit 34, the prior art network interface circuit 20 sends a transmission done signal by the medium access circuit 34. In other words, after accomplishing a transmission of a packet, the medium access circuit 34 has to wait for a period to make the memory access circuit 26 access the next packet data from the system memory 22. The next packet data is transmitted to the memory 28, the buffer 32, and the medium control module 30 sequentially, and then the medium access circuit 34 starts transmitting another packet to the network 12. Because there is still a period between an end of transmission of a packet and the start of transmission of the next packet, the efficiency of network transmission with the prior art network interface circuit 20 is lower, and this influences the efficiency when users access data from a network.
In the prior art, after the medium access circuit completely transmits a packet, the memory access circuit starts storing the next packet in the memory according to the transmission done signal. Therefore there is still a period between an end of transmission of a packet and the start of transmission of the next packet. This reduces efficiency of network transmission.